Electrically erasable and programmable non-volatile storage location

ABSTRACT

Electrically erasable and programmable non-volatile memory cell, which is formed with only one MOS transistor which is formed by a source-channel-drain junction, semi conductor substrate (1) of a first conductivity type has a drain region (2) and a source region (3) of a second conductivity type with a polarity opposite to that of the first conductivity type. A gate electrode (4), which is at a floating potential, is electrically insulated from the drain area (2) by a tunneling oxide (5) and from a channel region (9), which is located between the drain area and the source area (2, 3), by a gate oxide (5; 10). It and extends at least over a part of the channel region (9) and a part of the drain region (2) in the source-channel-drain direction. A control electrode (7) is electrically insulated from the gate electrode (4) by a coupling oxide (8).

BACKGROUND OF THE INVENTION

In applications for general control tasks, but in particular in smartcards, microcontrollers require non-volatile memories as programmemories and data memories. Particularly when used in battery-operatedportable data media, for example in the case of mobile datatransmissions and data processing, or with wire-free power supply, forexample in the case of contact-free smart cards, only programming anderasing methods having a low power consumption are acceptable, inparticular for the data memory. In the same way, the supply voltagesshould be less than 3 V. Since controllers and smart cards are subjectedto high pricing pressures, it is important for widespread use that theproduction process complexity for the non-volatile memories is low.

The FLOTOX-EEPROM cells which are widely used in smart cards nowadays,as are known for example from "Mikroelektronische Speicher"Microelectronic memory! by Dietrich Rhein and Heinz Freitag, SpringerPress, Vienna 1992, in particular on page 122, are distinguished by lowpower consumption since they are programmed and erased viaFowler-Nordheim tunnel currents. In consequence, the programmingvoltages can also easily be produced on the chip from low supplyvoltages, which may be less than 3 V. Such memories can be reprogrammedbyte by byte so that FLOTOX-EEPROM cells are particularly suitable fordata memories which are reprogrammed in operation. These FLOTOX-EEPROMcells comprise a selection transistor and a storage transistor andtherefore require a large cell area, so that only small-memories can beimplemented on a chip. In addition, as a result of the high requiredprogramming voltage of 15 to 20 V, the implementation of thehigh-voltage transistors to allow this programming voltage to beswitched is costly.

In contrast to EEPROMs, flash memories are implemented with-only onetransistor per memory cell so that considerably more complex memoriesthan with FLOTOX-EEPROM cells are possible here. However, they areprogrammed with hot charge carriers (channel hot electron: CHE). Thistype of programming requires high programming currents, which limit theminimal supply voltage to about 5 V. They cannot therefore be used asdata memories, which are intended to be reprogrammed in operation fromlow supply voltages or via contact-free power supplies. A split-gateflash EEPROM cell which is usual nowadays, is likewise illustrated anddescribed on page 126 of the book "Mikroelektronische Speicher"Microelectronic Memories!.

U.S. Pat. No. 5,294,819 also shows a one-transistor EEPROM cell, whichis formed with only one MOS transistor, which is formed by asource-channel-drain junction in which there are constructed in asemiconductor substrate of a first conductivity type a drain region anda source region of a second conductivity type and having a polarityopposite to that of the first conductivity type. The cell has a gateelectrode which is at a floating potential and is electrically insulatedfrom the drain area by a tunneling oxide and from a channel region,which is located between the drain area and the source area, by a gateoxide, and extends at least over a part of the channel region and a partof the drain region in the source-channel-drain direction, and a controlelectrode which is electrically insulated from the gate electrode by acoupling oxide.

There, both erasing and programming are carried out by means oftunneling currents, although use is made only of a high positive voltagewhich is applied either to the control gate or to the drain terminal ofthe transistor, in order to bring electrons to the control gate or takethem away. Owing to the use of only a high positive voltage, the lattermust have a large absolute value of approximately 18 volts, resulting inthe high outlay for insulation on the semiconductor chip.

Patent Abstracts of Japan, Vol. 15, No. 241 and Japanese referenceJP-A-3,074,881 likewise show a non-volatile memory cell having thedesign described above. There, a negative voltage is applied to thecontrol gate and a low voltage is applied to the drain electrode inorder to remove electrodes from the memory gate. However, it is notdisclosed how the electrons are brought to the memory gate.

SUMMARY OF THE INVENTION

It is thus the object of the present invention to specify a method foroperating an electrically erasable and programmable non-volatile memorycell which avoids the disadvantages of the prior art.

In general terms, the present invention is a method for operating anelectrically erasable and programmable non-volatile memory cell, whichis formed with only one MOS transistor which is formed by asource-channel-drain junction.

There are constructed in a semiconductor substrate of a firstconductivity type a drain region and a source region of a secondconductivity type that has a polarity opposite to that of the firstconductivity type.

A gate electrode is at a floating potential and is electricallyinsulated from the drain area by a tunneling oxide and from a channelregion, which is located between the drain area and the source area, bya gate oxide. The gate electrode extends at least over a part of thechannel region and a part of the drain region in thesource-channel-drain direction.

A control electrode is electrically insulated from the gate electrode bya coupling oxide.

In order to program the memory cell, a high negative voltage is appliedto the control electrode. The supply voltage is applied to the drainelectrode (D) and zero volts are applied to the source electrode.

In order to erase the memory cell, a high positive voltage is applied tothe control electrode, a negative voltage is applied to the sourceelectrode, and the drain electrode is not connected.

Advantageous developments of the present invention are as follows.

The gate electrode of the memory cell extends over the entire channelregion.

The oxide layer in the memory cell is divided over the channel regioninto a first gate oxide region, which couples the gate electrodecapacitively to the channel region, and into a second gate oxide region.The second gate oxide region couples a subregion of the controlelectrode capacitively to the channel region.

The tunneling oxide in the memory cell is thinner than the gate oxide.

The gate oxide in the memory cell extends into the region of thejunction between the drain area and the channel area, and partiallyoverlaps the drain area.

The MOS transistor is constructed in a well of the first conductivitytype, which well is arranged in a deep well of the second conductivitytype.

The MOS transistor is arranged together with a standard CMOS logiccircuit and/or a high-voltage circuit in a semiconductor substrate.

The memory cell on which the invention is based comprises only onetransistor, so that its space requirement is considerably smaller thanconventional FLOTOX-EEPROM cells. However, it is programmed and erasedin the same manner as such FLOTOX-EEPROM cells, by Fowler-Nordheimtunnel currents.

However, as a result of use according to the invention of negative andpositive voltages for programming and erasing, the magnitude of the highvoltages can be kept relatively low, so that the non-high-voltagecircuit parts need not be designed to withstand such high voltages,either, and they can thus be produced at a reduced manufacturing cost.In addition, the on-chip charging pump which is required to produce thehigh voltage may be of small size.

If the first conductivity type is the p-conductivity type and the MOStransistor which forms the cell is an n-channel transistor, the cell istypically programmed by applying a voltage of -12 V to its control gateand a voltage of +5 V to the drain, while the source is connected toearth. In consequence, in the region of the tunnelling oxide, that is tosay in the region in which the gate electrode, the so-called floatinggate which is at a floating potential, overlaps the drain region, chargecarriers tunnel through the tunnelling oxide with the result that thefloating gate is positively charged. In consequence, the thresholdvoltage of this MOS transistor is shifted to lower values. In order toerase a cell which has been programmed in such a manner, a voltage oftypically 12 V is applied to the control electrode and a voltage oftypically -6 V is applied to the source electrode, while the drainelectrode remains open. In consequence, charge carriers tunnel betweenthe floating gate and the source region as well as the channel region,so that the floating gate is discharged again and the threshold voltageof the transistor is shifted to higher values. The threshold voltagesare about 1 V for a programmed cell and about 5 V for a cell which isnot programmed. A voltage of about 3 V is therefore applied to thecontrol gate for reading, while a voltage of about 1 V is applied to thedrain, and a voltage of 0 V is applied to the source. A current willflow only in a programmed cell, and can be detected, for example, aslogic "1".

As a result of the simultaneous use according to the invention of apositive voltage and a negative voltage for programming and erasing amemory cell according to the invention, it is possible to dispense withan additional selection transistor, which necessitates a high spacerequirement, and nevertheless to be able to address each memory cellindividually. In the case of a conventional arrangement of the memorycells in a memory matrix, in which the gate connections of the memorycells are connected to the wordlines and the drain connections areconnected to the bitlines, all the memory cells whose gate connectionsare connected to this wordline are necessarily connected to a negativevoltage if said negative voltage is applied to a wordline. However, theonly memory cell which is programmed is that whose drain connection isconnected to a positive voltage. The condition that both voltages areapplied simultaneously only to a single memory cell can thus besatisfied by selection of only one wordline and only one bitline.

In the case of the memory cell according to the invention, the supplyvoltage is present, as a maximum, at the drain connection so that thesupply voltage is present, as a maximum, on the bitline which isconnected to the drain connection and thus on the evaluation circuits,and there is therefore no need to take special precautions forprotection of these evaluation circuits.

The memory cell according to the invention can be implemented in anadvantageous manner together with standard CMOS logic circuits on asemiconductor substrate, that is to say on a chip. It is also possibleto implement the high-voltage CMOS circuits, for switching the requiredpositive and negative high voltages, on the same semiconductorsubstrate, at the same time as well. Both the memory cells and thehigh-voltage circuits are for this purpose arranged in deep wells havinga polarity of the opposite conductivity type to the polarity of theconductivity type of the semiconductor substrate.

In a first configuration of a memory cell according to the invention,the floating gate extends in the source-channel-drain direction over theentire channel region as well as over a part of the drain region. Thisoverlapping region of the floating gate and the drain in this casedefines the tunnelling region during programming.

In a particularly advantageous configuration, the insulating oxide isthinner at least in a part of the overlapping region than over thechannel region. The tunnelling region is now defined by this thinnerregion. However, in order to avoid gate-field-induced drain leakage,during programming, it is particularly advantageous for the oxide to bethicker in the region of the pn-junction from the drain region to thechannel region than the tunnelling oxide.

In memory cells in which the floating gate covers the entire channelregion, the threshold voltage of the cell becomes negative in the eventof excessively long programming, so that deselection of such programmedcells during reading is prevented. This can be prevented by anadvantageous configuration of a so-called split gate cell. In this case,the floating gate extends only over part of the channel region, whilethe control electrode extends over the entire channel region and, indoing so, is capacitively coupled to the channel, in order to controlit, in the region where there is no longer any floating gate. With sucha split gate cell, the lower threshold voltage of the cell is limitedvia the series transistor formed from a control electrode and the gateoxide, even when the threshold voltage of the transistor part composedof the floating gate and gate oxide becomes negative.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention which are believed to be novel,are set forth with particularity in the appended claims. The invention,together with further objects and advantages, may best be understood byreference to the following description taken in conjunction with theaccompanying drawings, in the several Figures of which like referencenumerals identify like elements, and in which:

FIG. 1 shows a schematic illustration of a cross-section through amemory cell according to the invention,

FIG. 2 shows a schematic illustration of a cross-section through adevelopment of the memory cell according to the invention,

FIG. 3 shows a schematic illustration of the arrangement of such memorycells in a memory cell matrix, and

FIG. 4 shows the basic implementation, in schematic form, of the memoryfield, standard CMOS logic and high-voltage CMOS circuits in asemiconductor substrate.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a semiconductor substrate 1 of a first conductivity type,which is intended to be of the p-type, for example. In thissemiconductor substrate 1, a drain region 2 and a source region 3 of oneconductivity type have the opposite polarity to the conductivity type ofthe semiconductor substrate 1, that is to say to the n-type in thepresent example. The transistor of this memory cell is correspondinglyan n-channel transistor. The drain region 2 is provided with a drainconnection D and the source region 3 is provided with a sourceconnection S. An oxide layer is constructed as an electrical insulatinglayer over the drain region 2 and the source region 3, and the channelregion 9 which is located between these regions. A gate electrode 4,which is at an electrically floating potential, is constructed over thisoxide layer 5, 6. This is normally called a floating gate. It extends inthe manner according to the invention in the source-channel-draindirection of the MOS transistor over the channel region and at least apart of the drain region 2. The region of the oxide layer between thefloating gate 4 and the channel region is called the gate oxide 5, andthe region of the oxide layer between the floating gate 4 and the drainregion 2 is called the tunnelling oxide 6. In the case of thedevelopment of the invention illustrated in FIG. 1, the tunnelling oxide6 is thinner than the gate oxide S. It is particularly advantageous ifthe tunnelling oxide 6, as is illustrated in FIG. 1, has the samethickness in the region of the pn-junction from the drain area 2 to thechannel area 9 as the gate oxide 5, as the result of which anygate-field-induced drain leakage current is prevented or at leastreduced. For applications in which a higher drain leakage current ofthis type can be accepted during programming, the arrangement in FIG. 1can be simplified in that the thicknesses of the tunnelling oxide 6 andof the gate oxide 5 are selected to be the same. A number of processsteps are omitted in the production method for this simplified memorycell. A control electrode 7 is arranged above the gate electrode and thefloating gate 4 and is electrically insulated from the floating gate 4by a coupling oxide 8. This control electrode 7 is connected to the gateconnecting G.

FIG. 2 shows a development of the memory cell according to FIG. 1,identical parts having the same reference numbers. A split gate cell isillustrated. In this case, the floating gate 4 extends only over part ofthe channel region 9. In consequence, the control electrode 7 can becapacitively coupled to the channel region 9 over a subregion 10 of thegate oxide, and can in consequence control this channel region 9. Thismeasure compensates for the effects of the negative threshold voltageduring "reprogramming".

FIG. 3 shows a schematic illustration of memory cells according to theinvention in a memory cell matrix. The memory cell matrix is organizedin the form of wordlines . . . WL_(n), WL_(m) . . . and bitlines . . .BL_(k), BL_(l) . . . The memory cells are each connected by their gateconnection G to one of the wordlines . . . WL_(n), WL_(m) . . . , and bytheir drain connection D to one of the bitlines . . . BL_(k), BL_(l) . .. The source connections S of all the memory cells are connected to asource line SL. There may, of course, also be a plurality of sourcelines, which are then each connected to only one group of memory cellsource connections S.

In the case of a memory cell which is formed using an NMOS transistor,it is necessary for programming purposes to apply a high negativeprogramming voltage to the control electrode, that is to say to the gateconnection G of the memory cell. According to FIG. 3, this means thatthis programming voltage must be applied to a wordline WL_(n). However,this means that this programming voltage is simultaneously applied toall the other memory cells whose gate connections are connected to thiswordline.

However, in order that programming actually takes place in the case of amemory cell according to the invention, a positive voltage must beapplied to the drain connection D at the same time that the highnegative programming voltage is applied to the gate connection G. As canonce again be seen from FIG. 3, this positive voltage must be applied toa bitline BL_(k), as a result of which this positive voltage is in turnapplied to all the drain connections D of the memory cells which areconnected to this bitline BL_(k). However, programming takes placeonly-when simultaneously a negative programming voltage is present atthe gate connection and a positive voltage is present at the drainconnection. If only one wordline and only one bitline have beenselected, this condition is satisfied only for a single memory cell.Thus, in the case of a memory constructed with memory cells according tothe invention, each memory cell can be addressed individually. It is, ofcourse, also possible to program a plurality of memory cellssimultaneously by addressing a plurality of wordlines and/or a pluralityof bitlines simultaneously.

A high positive voltage must be applied to the gate connection of amemory cell, and a negative voltage to the source connection, forerasing. If all the source connections are connected to a source line,and when only one wordline is selected, on which the high positivevoltage is present, the smallest number of memory cells which are erasedin one go is the number of memory cells which are connected to awordline. This measure considerably speeds up the erasure process.

In the case of the implementation of the electrically erasable andprogrammable non-volatile memory described above, together with CMOSlogic, special precautions have to be taken in particular because of thehigh positive and negative voltages which arise. The precautions areillustrated in a schematic manner in FIG. 4. Assuming a p-conductivitysemiconductor substrate, the NMOS and PMOS field-effect transistors forthe logic are produced in the p-substrate in an n-well. In consequence,the CMOS logic is design-compatible with standard CMOS circuits. Athicker gate oxide is necessary for the high voltage CMOS transistorsand, in addition, the NMOS transistors for switching negative voltagesare placed, insulated from the substrate, in a p-well within a deepn-well. The high-voltage PMOS transistors are located in the n-well. Ifthe requirements placed on the switching speed of the logic are notsevere, the high-voltage and logic transistors can also be implementedusing the same (thicker) oxide thickness. The memory cells are produced,insulated from the substrate, in a p-well within a deep n-well. It isthus possible to connect a negative voltage to the common source linewithout influencing the logic section.

The use of positive and negative voltages limits the magnitude of theprogramming voltages which occur to about 12 V, so that the high-voltagesections may be designed only for this magnitude. As a result of the useof the insulated p-well within the deep n-well, negative voltages can beprocessed without having to revert to voltage invertors and PMOS sourcefollowers in the high-voltage section. In the memory cell field, theinsulated p-well has the advantage that the common source line can beconnected to a negative voltage without influencing the CMOS logicsection. The positive and negative programming voltages can easily beproduced on the chip by charging pumps, as a result of the low powerconsumption of the Fowler-Nordheim programming.

The individual components in FIG. 4 are isolated from one another byfield-oxide regions FO. The gate electrodes G of the CMOS logic circuitsand of the high-voltage CMOS circuits are admittedly illustrated at thesame distance from the channel region in FIG. 4, but, in practice, iffast CMOS logic is required, the oxide thicknesses under the gateelectrodes G are selected to be different. The floating gate FG and thecontrol gate SG are illustrated in a schematic manner in the cell of thememory field illustrated in FIG. 4.

The invention is not limited to the particular details of the methoddepicted and other modifications and applications are contemplated.Certain other changes may be made in the above described method withoutdeparting from the true spirit and scope of the invention hereininvolved. It is intended, therefore, that the subject matter in theabove depiction shall be interpreted as illustrative and not in alimiting sense.

What is claimed is:
 1. A method for operating an electrically erasableand programmable non-volatile memory cell, which is formed with only oneMOS transistor which is formed by a source-channel-drain junction,comprising the steps of:constructing in a semiconductor substrate of afirst conductivity type, a drain region and a source region of a secondconductivity type having a polarity opposite to that of the firstconductivity type: constructing a gate electrode which is at a floatingpotential, and which is electrically insulated from the drain area by atunneling oxide and from a channel region, which is located between thedrain area and the source area, by a gate oxide, and extends at leastover a part of the channel region and a part of the drain region in asource-channel-drain direction; constructing a control electrode whichis electrically insulated from the gate electrode by a coupling oxide;applying, for programming the memory cell, a high negative voltage tothe control electrode, a supply voltage to the drain electrode and zerovolts to the source electrode; and applying, for erasing the memorycell, a high positive voltage to the control electrode, a negativevoltage to the source electrode, and disconnecting the drain electrode.2. The method according to claim 1, wherein the gate electrode of thememory cell extends over the entire channel region (9).
 3. The methodaccording to claim 1, wherein an oxide layer in the memory cell isdivided over the channel region into a first gate oxide region, whichcapacitively couples the gate electrode to the channel region, and intoa second gate oxide region, the second gate oxide region capacitivelycoupling a subregion of the control electrode to the channel region. 4.The method according to claim 1, wherein the tunneling oxide in thememory cell is thinner than the gate oxide.
 5. The method according toclaim 4, wherein the gate oxide in the memory cell extends into a regionof a junction between the drain area and the channel area, and partiallyoverlaps the drain area.
 6. The method according to claim 1, wherein theMOS transistor is constructed in a well of the first conductivity type,which well is arranged in a deep well of the second conductivity type.7. The method according to claim 6, wherein the MOS transistor isarranged together with at least one of a standard CMOS logic circuit anda high-voltage circuit in a semiconductor substrate.